In high-speed optical communications networks, optical signals received through an optical fiber link suffer inter-symbol interference (ISI) due to, among other things, chromatic dispersion (CD) and polarization mode dispersion (PMD). In the presence of severe inter-symbol interference (ISI), clock recovery using conventional clock phase detector algorithms can fail. For example for the optical channel, chromatic dispersion (CD) and polarization mode dispersion (PMD) can dramatically reduce the clock phase sensitivity such that the phase lock condition is lost. An approach for deriving clock phase after signal equalization (e.g. for distortion compensation) is known from K. H. Mueller and M. Muller, “Timing Recovery in Digital Synchronous Data Receivers,” IEEE Trans. Comm., Vol. COM-24, No. 5, May 1976.
FIG. 1 illustrates a coherent optical receiver known, for example, from Applicant's co-pending U.S. patent application Ser. No. 11/551,367 filed Oct. 20, 2006, and U.S. patent application Ser. Nos. 11/315,342 and 11/315,345, both of which were filed Dec. 23, 2005. The entire contents of U.S. patent application Ser. Nos. 11/551,367, 11/315,342 and 11/315,345 are incorporated herein by reference.
As may be seen in FIG. 1, an inbound optical signal is received through an optical link 2, split into orthogonal received polarizations by a Polarization Beam Splitter 4, and then mixed with a Local Oscillator (LO) signal 6 by a conventional 90° optical hybrid 8. The composite optical signals emerging from the optical hybrid 8 are supplied to respective photodetectors 10, which generate corresponding analog electrical signals. The photodetector signals are sampled by respective Analog-to-Digital (A/D) converters 12 to yield raw multi-bit digital signals IX, QX and IY, QY corresponding to In-phase (I) and Quadrature (Q) components of each of the received polarizations.
From the A/D converter 12 block, the respective n-bit signals IX, QX and IY, QY of each received polarization are supplied to an agile signal equalizer 14 which operates to compensate chromatic dispersion and polarization rotation impairments. In general, the signal equalizer 14 comprises a respective dispersion compensation block 16 for each of the X- and Y-polarizations, and a polarization compensation block 18. The dispersion compensation blocks 16 have a width sufficient to enable compensation of moderate-to-severe dispersion (e.g. on the order of 10000 ps/nm) based on a set of dispersion compensation coefficients 20, and generate respective intermediate vectors {TAX} and {TAY}. These intermediate vectors {TAX} and {TAY} are then input to the polarization compensation block 18, which uses a set of polarization compensation vectors HXX, HXY, HYY and HYX to impose a phase rotation which compensates polarization impairments of the optical signal, and so de-convolve the transmitted symbols from the raw digital sample streams IX, QX, and IY, QY generated by the A/D converters 12. The compensated signals 22 output from the equalizer 14 represent multi-bit estimates X′(n) and Y′(n) of the symbols encoded on each transmitted polarization of the received optical signal. These symbol estimates 22 X′(n), Y′(n), are supplied to a carrier recovery block 24 for LO frequency control, symbol detection and data recovery, such as described in Applicant's co-pending U.S. patent application Ser. No. 11/366,392 filed Mar. 2, 2006.
As shown in FIG. 1, a Least Mean Squares (LMS) update block 26 computes the polarization compensation vectors HXX, HXY, HYY and HYX based on the intermediate vectors {TAX} and {TAY}, as well as symbol phase and error information received from the carrier recovery block 24. As described in Applicant's co-pending U.S. patent application Ser. No. 11/551,367, the polarization compensation vectors HXX, HXY, HYY and HYX are updated at a sufficiently high rate to enable tracking, and therefore compensation, of polarization rotation transients at speeds on the order of 50 kHz.
In the receiver of FIG. 1, clock recovery can be performed as described in Applicant's co-pending U.S. patent application Ser. Nos. 11/315,342 and 11/315,345. Thus, with reference to FIG. 2, respective Upper Side Band (USB) and Lower Side Band (LSB) signals for each polarization are tapped from the output of the dispersion compensators 16 (i.e. the intermediate vectors {TAX} and {TAY}) and supplied to a clock recovery circuit 28 comprising an optimization block 30, a phase detector 32, loop filter 34 and an Voltage controlled Oscillator (VCO) 36. The optimization block 30 implements a polarization compensation function, based on a set of filter coefficients. In the systems of U.S. patent application Ser. Nos. 11/315,342 and 11/315,345, these filter coefficients are angle θ(n+1) and phase φ(n+1) filter coefficients generated by a coefficient calculator (not shown). However, because both the optimization block 28 and the polarization compensator 18 perform similar functions, the polarization compensation vectors HXX, HXY, HYY and HYX computed by the LMS update block 26 can be used for this purpose, as shown in FIG. 2. The signal appearing at the output of the optimization block 30 is then supplied to the clock phase detector 32 and the phase detection result is passed to the loop filter 34, which supplies respective control signals to coarse (C) and fine (F) tuning ports of the voltage controlled Oscillator (VCO) 36. The output of the VCO 36 is used to drive the A/D converters 12, signal equalizer 14 and the carrier recovery block 22. As described in Applicant's co-pending U.S. patent application Ser. Nos. 11/315,342 and 11/315,345, the phase detector 32 also generates a lock detection function ƒ(θp, φp), which can be used to detect a signal lock condition.
As may be appreciated, the signal path from the A/D converters 12, through the clock recovery circuit 28 and back to the A/D converters 12 defines a digital Phase Locked Loop (PLL) which tunes the VCO output to phase and frequency match symbols modulated onto the received optical signal. Similarly, the signal path from the dispersion compensators 16, through the polarization compensator 18, the carrier recovery block 24, LMS update block 26 and back to the polarization compensator 18 forms an equalizer adaptation loop which adaptively optimizes the compensation vectors HXX, HXY, HYY and HYX.
The coherent optical receiver of FIGS. 1 and 2 is capable of digital clock recovery from a high-speed (e.g. symbol rates above 10 Gbaud) optical signal composed of two independently modulated orthogonal polarizations, even in the presence of moderate to severe ISI due to chromatic dispersion (CD) and polarization mode dispersion (PMD), and polarization transients on the order of 50 kHz.
As noted above, because both the polarization compensator 18 and the optimization block 30 perform similar functions, the compensation vectors HXX, HXY, HYY and HYX computed by the LMS update block 26 can be used for both signal equalization and clock phase detection. This arrangement in beneficial in that it eliminates the need for separate angle θ(n+1) and phase φ(n+1) filter coefficient computation blocks, and therefore reduces the cost of the receiver. However, this arrangement suffers a limitation in that the equalizer adaptation loop can interact with the clock recovery PLL to yield a double nested loop. In some cases, this interaction can lead to a random walk behaviour of the compensation vectors HXX, HXY, HYY and HYX and the VCO clock phase. Over time, this random walk behaviour can drive the clock phase to one side of the eye opening and thereby severely limit the ability of the equalizer 14 to compensate ISI. In extreme cases, this can lead to severe performance penalties or even system breakdown.
Accordingly, techniques for separating adaptation and clock recovery loops are highly desirable.